As product performance requirements continue to increase, manufacturers continue providing semiconductor circuits that have improved performance characteristics. For example, as data rates increase, manufacturers provide more precise filter and oscillator circuits. Usually, these analog circuits, including phase locked loops (PLL), voltage controlled oscillators (VCO), and analog to digital converters, are much more sensitive than digital circuits to noise, component matching, and other short distance variations. In addition, the analog circuits often require calibration to overcome fabrication tolerances.
Typically, the process of fabricating semiconductor circuits includes depositing multiple layers of material, such as semiconductor, dielectric, and conductive material, on a semiconductor wafer. Each of the layers is patterned and etched to form active devices, resistors, capacitors, and other components, which are interconnected to form analog and/or digital circuits. Often, plasma processing is used in depositing materials, etching, pre-cleaning, photo-resist stripping, and ion implantation. Some components are directly exposed to plasma and suffer plasma induced damage, including degradation of dielectric layers. Also, some components are damaged via contamination during processing. The plasma induced damage and/or contamination leads to soft breakdowns and increased leakage currents as compared to the leakage currents of undamaged material.
Circuits are built to operate over a range of fabrication tolerances. Often, one or more calibrations are performed to overcome variations related to fabrication tolerances and to overcome increased leakage currents due to damage that occurred during the fabrication process. If component properties remain unchanged over time, the circuits continue to operate properly. However, time dependent variations in component properties can be fatal to the stability and functioning of the circuits.
The component properties of undamaged components, such as a perfect dielectric film, remain stable over time, but the component properties of damaged components vary or are unstable over time. The damage to dielectric films during the fabrication process leads to current fluctuations, referred to as random telegraphic noise (RTN). In literature, RTN frequently refers to fluctuations of current between the source and drain of a field effect transistor (FET) due to charge traps in the dielectric close to the inversion channel that randomly change their filling state. Herein, RTN refers to the leakage current through the dielectric film. Usually, these current fluctuations are related to damage such as plasma induced damage and/or contamination that occurs during wafer processing. RTN can be fatal, such that it leads to soft failures in the circuits. Since RTN shows up on an irregular basis, detecting RTN can be difficult and may require observation over time, which increases cost. Also, RTN may not be detected during the observation period and show up later.
To reduce circuit failures, the fabrication process can be optimized to reduce plasma induced damage and contamination. However, excessive characterization efforts and changes to the fabrication process can result in a drop in production yields and increase costs. In addition, screening via stability measurements increases costs.
For these and other reasons there is a need for the present invention.